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????????????????????????????????????????????????????????????????? maxim integrated products 1 simplified operating circuit 19-6171; rev 1; 4/12 ordering information appears at end of data sheet. modelgauge is a trademark of maxim integrated products, inc. general description the max17048/max17049 ics are tiny, micropower current fuel gauges for lithium-ion (li+) batteries in hand - held and portable equipment. the max17048 operates with a single lithium cell and the max17049 with two lithium cells in series. the ics use the sophisticated li+ battery-modeling algorithm modelgauge k to track the battery relative state-of-charge (soc) continuously over widely varying charge and discharge conditions. the modelgauge algorithm eliminates current-sense resistor and battery-learn cycles required in traditional fuel gauges. temperature compensation is implemented using the system microcontroller. the ics automatically detect when the battery enters a low-current state and switches into a low-power 4 f a hibernate mode, while still providing accurate fuel gauging. the ics automatically exit hibernate mode when the system returns to active state. on battery insertion, the ics debounce initial voltage measurements to improve the initial soc estimate, thus allowing them to be located on system side. soc, voltage, and rate information is accessed using the i 2 c interface. the ics are available in a tiny 0.9mm x 1.7mm, 8-bump wafer-level package (wlp), or a 2mm x 2mm, 8-pin tdfn package. applications wireless handsets smartphones/pdas tablets and handheld computers portable game players e-readers digital still and video cameras portable medical equipment features and benefits s max17048: 1 cell, max17049: 2 cells s precision 7.5m v/cell voltage measurement s modelgauge algorithm ? provides accurate state-of-charge ? compensates for temperature/load variation ? does not accumulate errors, unlike coulomb counters ? eliminates learning ? eliminates current-sense resistor s ultra-low quiescent current ? 4a hibernate, 23a active ? fuel gauges in hibernate mode ? automatically enters and exits hibernate mode s reports charge and discharge rate s battery-insertion debounce ? best of 16 samples to estimate initial soc s programmable reset for battery swap ? 2.28v to 3.48v range s configurable alert indicator ? low soc ? 1% change in soc ? battery undervoltage/overvoltage ? vreset alert s i 2 c interface s 8-bit otp id register (contact factory) only one external component v dd alrt sda scl cell qstrt ctg gnd system p max17048 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
????????????????????????????????????????????????????????????????? maxim integrated products 2 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics cell to gnd ......................................................... -0.3v to +12v v in , scl, sda, alrt to gnd ................................. -0.3v to +6v continuous sink current, sda, alrt ................................ 20ma operating temperature range .......................... -40 n c to +85 n c storage temperature range ............................ -55 n c to +125 n c lead temperature (tdfn only) (soldering, 10s) ........... +300 n c soldering temperature (reflow) tdfn ............................................................................ +260 n c wlp ............................................................................. +240 n c absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (v in = 2.5v to 4.5v, t a = -20 n c to +70 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 1) parameter symbol conditions min typ max units supply voltage v in (note 2) 2.5 4.5 v fuel-gauge soc reset (vreset register) v rst configuration range, in 40mv steps 2.28 3.48 v trimmed at 3v 2.85 3.0 3.15 v data i/o pins scl, sda, alrt (note 2) -0.3 +5.5 v supply current i dd0 sleep mode, t a p +50 n c 0.5 2 f a hibernate mode, reset comparator enabled (vreset.dis = 0) 3 5 hibernate mode, reset comparator disabled (vreset.dis = 0) 4 i dd1 active mode 23 40 time base accuracy t err active, hibernate modes (note 3) -3.5 q 1 +3.5 % adc sample period active mode 250 ms hibernate mode 45 s voltage error v err v cell = 3.6v, t a = +25 n c (note 4) -7.5 +7.5 mv/cell -20 +20 voltage-measurement resolution 1.25 mv/cell voltage-measurement range max17048: v in pin 2.5 5 v max17049: cell pin 5 10 sda, scl, qstrt input logic-high v ih 1.4 v sda, scl, qstrt input logic-low v il 0.5 v sda, alrt output logic-low v ol i ol = 4ma 0.4 v sda, scl bus low-detection current i pd v sda = v scl = 0.4v (note 5) 0.2 0.4 f a bus low-detection timeout t sleep (note 6) 1.75 2.5 s
????????????????????????????????????????????????????????????????? maxim integrated products 3 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics note 1: specifications are 100% tested at t a = +25 n c. limits over the operating range are guaranteed by design and characterization. note 2: all voltages are referenced to gnd. note 3: test is performed on unmounted/unsoldered parts. note 4: the voltage is trimmed and verified with 16x averaging. note 5: this current is always present. note 6: the ic enters shutdown mode after scl < v il and sda < v il for longer than 2.5s. note 7: timing must be fast enough to prevent the ic from entering sleep mode due to bus low for period > t sleep . note 8: f scl must meet the minimum clock low time plus the rise/fall times. note 9: the maximum t hd:dat has to be met only if the device does not stretch the low period (t low ) of the scl signal. note 10: this device internally provides a hold time of at least 100ns for the sda signal (referred to the v ih,min of the scl signal) to bridge the undefined region of the falling edge of scl. note 11: filters on sda and scl suppress noise spikes at the input buffers and delay the sampling instance. note 12: c b is total capacitance of one bus line in pf. electrical characteristics (i 2 c interface) (2.5v < v batt < 4.5v, t a = -20 n c to +70 n c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units scl clock frequency f scl (note 7) 0 400 khz bus free time between a stop and start condition t buf 1.3 f s start condition (repeated) hold time t hd:sta (note 8) 0.6 f s low period of scl clock t low 1.3 f s high period of scl clock t high 0.6 f s setup time for a repeated start condition t su:sta 0.6 f s data hold time t hd:dat (notes 9, 10) 0 0.9 f s data setup time t su:dat (note 9) 100 ns rise time of both sda and scl signals t r 20 + 0.1c b 300 ns fall time of both sda and scl signals t f 20 + 0.1c b 300 ns setup time for stop condition t su:sto 0.6 f s spike pulse widths suppressed by input filter t sp (note 11) 0 50 ns capacitive load for each bus line c b (note 12) 400 pf scl, sda input capacitance c b,in 60 pf
????????????????????????????????????????????????????????????????? maxim integrated products 4 typical operating characteristics (t a = +25 n c, battery is sanyo uf504553f, unless otherwise noted.) figure 1. i 2 c bus timing diagram quiescent current vs. supply voltage (hibernate mode) max17048 toc01 v cell (v) quiescent current (a) 4.0 3.5 3.0 0 2.5 4.5 t a = +70c 1 2 3 4 5 t a = -20c t a = +25c c rate accuracy max17048 toc04 c rate (%/hr) -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 time (hr) 6 4 2 0 -2 -4 8 max17048 c rate measured c rate enter hibernate mode automatically max17048 toc05 time (min) current (i_batt ma, i_dd ua) v batt (v) 15 10 5 0 3.70 100 200 300 400 500 600 -100 02 0 v batt i batt i dd1 i dd0 3.75 3.80 3.85 3.90 3.95 4.00 3.65 5 10 15 20 25 30 35 40 quiescent current vs. supply voltage (active mode) max17048 toc02 v cell (v) quiescent current (a) 4.0 3.5 3.0 0 2.5 4.5 t a = +70c t a = -20c t a = +25c voltage adc error vs. temperature max17048 toc03 temperature (c) voltage adc error (mv/cell) 55 40 -5 10 25 -15 -10 -5 0 5 10 15 20 -20 -20 70 v cell = 3.6v v cell = 2.5v v cell = 4.5v sda scl t f t low t hd:sta t hd:dat t su:sta t su:sto t su:dat t hd:sta t sp t r t buf t r t f ss r p s max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics
????????????????????????????????????????????????????????????????? maxim integrated products 5 typical operating characteristics (continued) (t a = +25 n c, battery is sanyo uf504553f, unless otherwise noted.) exit hibernate mode automatically max17048 toc06 time (min) current (i_batt ma, i_dd ua) v batt (v) 8 24 6 0 3.70 100 200 300 400 500 600 -100 01 0 v batt i batt i dd1 i dd0 3.75 3.80 3.85 3.90 3.95 4.00 3.65 zigzag pattern soc accuracy (1/3) max17048 toc08 soc (%) error (%) reference soc modelgauge error 25 50 75 100 0 -5 0 5 10 -10 time (hr) 80 60 40 20 0 100 zigzag pattern soc accuracy (3/3) max17048 toc10 time (hr) soc (%) error (%) 103 101 99 reference soc modelgauge error 97 25 50 75 100 0 -5 0 5 10 -10 95 105 soc accuracy t a = 20c, hibernate mode max17048 toc07 time (hr) soc (%) error (%) 8 6 4 reference soc modelgauge error 2 25 50 75 100 0 -5 0 5 10 -10 -4 -2 01 0 zigzag pattern soc accuracy (2/3) max17048 toc09 time (hr) soc (%) error (%) 8 6 4 reference soc modelgauge error 2 25 50 75 100 0 -5 0 5 10 -10 01 0 max17048 toc11 0a 0v 0v 0v 4ms/div debounce completed debounce begins v cell ocv battery-insertion debounce/ ocv acquisition max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics
????????????????????????????????????????????????????????????????? maxim integrated products 6 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics pin / bump descriptions pin / bump configurations pin/bump name function tdfn wlp 1 a1 ctg connect to ground 2 a2 cell connect to the positive battery terminal. max17048: not internally connected. max17049: voltage sense input. 3 a3 v dd power-supply input. bypass with 0.1 f f to gnd. max17048: voltage sense input. connect to positive battery terminal. max17049: connect to regulated power-supply voltage. 4 a4 gnd ground. connect to negative battery terminal. 5 b4 alrt open-drain, active-low alert output. optionally connect to interrupt input of the system microcontroller. 6 b3 qstrt quick-start input. allows reset of the device through hardware. connect to gnd if not used. 7 b2 scl i 2 c clock input. scl has an internal pulldown (i pd ) for sensing disconnection. 8 b1 sda open-drain i 2 c data input/output. sda has an internal pulldown (i pd ) for sensing disconnection. ep exposed pad (tdfn only). connect to gnd. 1 + 34 86 5 sd aq strt alrt max17048 max17049 2 7 sc l ctgv dd gnd cell tdfn top view (pad side down) a1 a2 a3 a4 b1 b2 b3 b4 + top view (bump side down) max17048 max17049 wlp ctgc ellv dd gnd sda scl qstrt alrt
????????????????????????????????????????????????????????????????? maxim integrated products 7 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics detailed description modelgauge theory of operation the max17048/max17049 ics simulate the internal, nonlinear dynamics of a li+ battery to determine its soc. the sophisticated battery model considers impedance and the slow rate of chemical reactions in the battery (figure 2). modelgauge performs best with a custom model, obtained by characterizing the battery at multiple dis - charge currents and temperatures to precisely model it. at power-on reset (por), the ics have a preloaded rom model that performs well for some batteries. fuel-gauge performance in coulomb counter-based fuel gauges, soc drifts because offset error in the current-sense adc measure - ment accumulates over time. instantaneous error can be very small, but never precisely zero. error accumulates over time in such systems (typically 0.5%C2% per day) and requires periodic corrections. some algorithms cor - rect drift using occasional events, and until such an event occurs the algorithms error is boundless: ? reaching predefined soc levels near full or empty ? measuring the relaxed battery voltage after a long period of inactivity ? completing a full charge/discharge cycle modelgauge requires no correction events because it uses only voltage, which is stable over time. as tocs 8, 9, and 10 show, modelgauge remains accurate despite the absence of any of the above events; it neither drifts nor accumulates error over time. to correctly measure performance of a fuel gauge as experienced by end-users, exercise the battery dynami - cally. accuracy cannot be fully determined from only simple cycles. battery voltage and state-of-charge open-circuit voltage (ocv) of a li+ battery uniquely determines its soc; one soc can have only one value of ocv. in contrast, a given v cell can occur at many dif - ferent values of ocv because v cell is a function of time, ocv, load, temperature, age, and impedance, etc.; one value of ocv can have many values of v cell . therefore, one soc can have many values of v cell , so v cell can - not uniquely determine soc. figure 3 shows that v cell = 3.81v occurs at 2%, 50%, and 72% soc. even the use of sophisticated tables to consider both voltage and load results in significant error due to the load transients typically experienced in a system. during charging or discharging, and for approximately 30min after, v cell and ocv differ substantially, and v cell has been affected by the preceding hours of battery activity. modelgauge uses voltage comprehensively. figure 2. block diagram figure 3. immediate battery voltage is not state-of-charge immediate battery voltage is not state-of-charge time (hours) soc v cell 100% 80% 60% 40% 20% 0% 012345678 3.4v 3.6v 3.8v 4.0v 4.2v 3.2v 3.81v = 2% v cell soc 3.81v = 72% 3.81v = 50% 3.81v state machine (soc, rate) 2-wire interface ic ground time base (32khz) adc (v cell ) voltage reference bias gnd cell v dd scl sda alrt qstrt ctg max17048 max17049
????????????????????????????????????????????????????????????????? maxim integrated products 8 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics temperature compensation for best performance, the host microcontroller must measure battery temperature periodically, and compen - sate the rcomp modelgauge parameter accordingly, at least once per minute. each custom model defines constants rcomp0, tempcohot, and tempcocold. to calculate the new value of config.rcomp: if temperature > +20c: rcomp = rcomp0 + (20c - temperature) x tempcohot if temperature < +20c: rcomp = rcomp0 + (20c - temperature) x tempcocold impact of empty-voltage selection most applications have a minimum operating voltage below which the system immediately powers off (empty voltage). when characterizing the battery to create a cus - tom model, choose empty voltage carefully. as shown in figure 4, capacity unavailable to the system increases at an accelerating rate as empty voltage increases. to ensure a controlled shutdown, consider including operating margin into the fuel gauge based on some low threshold of soc, for example shutting down at 3% or 5%. this utilizes the battery more effectively than adding error margin to empty voltage. battery insertion when the battery is first inserted into the system, the fuel-gauge ic has no previous knowledge about the bat - terys soc. assuming that the battery is relaxed, the ic translates its first v cell measurement into the best initial estimate of soc. initial error caused by the battery not being in a relaxed state diminishes over time, regardless of loading following this initial conversion. while soc estimated by a coulomb counter diverges, modelgauge soc converges, correcting error automatically as illus - trated in figure 5; initial error has no long-lasting impact. battery insertion debounce any time the ic powers on or resets (see the vreset/id register (0x18) section), it estimates that ocv is the maximum of 16 v cell samples (1ms each, full 12-bit resolution). ocv is ready 17ms after battery inser - tion, and soc is ready 175ms after that. figure 4. increasing empty voltage reduces battery capacity figure 5. modelgauge heals error automatically longer battery relaxation improves initial accuracy relaxation time before insertion (minutes) initial voltage error (mv) soc error (%) 0 -10 -20 0 -5 -10 0.1 11 0 100 1000 soc erro r voltage erro r modelgauge heals error automatically over time time after insertion (minutes ) soc (%) 0 -5 -10 30 45 15 0 02 04 06 08 0 relaxed soc reference soc relaxed error unrelaxed error unrelaxed soc capacity lost (%) 60 50 40 30 20 10 0 target empty voltage (v) 3.0 3.1 3.2 3.3 3.4 3.5 c/ 3 load c/ 10 load
????????????????????????????????????????????????????????????????? maxim integrated products 9 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics battery swap detection if v cell falls below v rst , the ic quick-starts when v cell returns above v rst . this handles battery swap; the soc of the previous battery does not affect that of the new one. see the quick-start and vreset/id register (0x18) sections. quick-start if the ic generates an erroneous initial soc, the battery insertion and system powerup voltage waveforms must be examined to determine if a quick-start is necessary, as well as the best time to execute the command. the ic samples the maximum v cell during the first 17ms. see the battery insertion debounce section. unless v cell is fully relaxed, even the best sampled voltage can appear greater or less than ocv. therefore, quick-start must be used cautiously. most systems should not use quick-start because the ics handle most startup problems transparently, such as intermittent battery-terminal connection during insertion. if battery voltage stabilizes faster than 17ms, as illus - trated in figure 6, then do not use quick-start. the quick-start command restarts fuel-gauge calcula - tions in the same manner as initial power-up of the ic. if the system power-up sequence is so noisy that the initial estimate of soc has unacceptable error, the sys - tem microcontroller might be able to reduce the error by using quick-start. a quick-start is initiated by a rising edge on the qstrt pin, or by writing 1 to the quick-start bit in the mode register. power-on reset (por) por includes a quick-start, so only use it when the battery is fully relaxed. see the quick-start section. this command restores all registers to their default values. after this command, reload the custom model. see the cmd register (0xff) section. hibernate mode the ics have a low-power hibernate mode that can accurately fuel gauge the battery when the charge/ discharge rate is low. by default, the device automati - cally enters and exits the hibernate mode according to the charge/discharge rate, which minimizes quiescent current (below 5 f a) without compromising fuel-gauge accuracy. the ics can be forced into hibernate or active modes. force the ic into hibernate mode to reduce power consumption in applications with less than c/4-rate maximum loading. for applications with higher loading, maxim recommends the default configuration of automatic control of hibernate mode. in hibernate mode, the device reduces its adc conver - sion period and soc update to once per 45s. see the hibrt register (0x0a) section for details on how the ic automatically enters and exits hibernate mode. figure 6. insertion waveform not requiring quick-start command figure 7. insertion waveform requiring quick-start command steady system load begins v cell has fully relaxed time v cell initial sample debounce window time v cell initial sample debounce window quick-start during this time span steady system load begins best time to quick-start v ce ll ha s fully relaxed
???????????????????????????????????????????????????????????????? maxim integrated products 10 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics alert interrupt the ics can interrupt a system microcontroller with five configurable alerts (see table 1). all alerts can be disa - bled or enabled with software. when the interrupt occurs, the system microcontroller can determine the cause from the status register. when an alert is triggered, the ic drives the alrt pin logic-low and sets config.alrt = 1. the alrt pin remains logic-low until the system software writes config.alrt = 0 to clear the alert. the alert function is enabled by default, so any alert can occur immediately upon power-up. entering sleep mode clears no alerts. sleep mode in sleep mode, the ic halts all operations, reducing cur - rent consumption to below 1 f a. after exiting sleep mode, the ic continues normal operation. in sleep mode, the ic does not detect self-discharge. if the battery changes state while the ic sleeps, the ic cannot detect it, causing soc error. wake up the ic before charging or discharging. to enter sleep mode, write mode.ensleep = 1 and either: u hold sda and scl logic-low for a period for t sleep . a rising edge on sda or scl wakes up the ic. u write config.sleep = 1. to wake up the ic, write config.sleep = 0. other communication does not wake up the ic. por does wake up the ic. applications which can tolerate 4 f a should use hibernate rather than sleep mode. register summary all registers must be written and read as 16-bit words; 8-bit writes cause no effect. any bits marked x (dont care) or read only must be written with the rest of the register, but the value written is ignored by the ic. the values read from dont care bits are undefined. calculate the registers value by multiplying the 16-bit word by the registers lsb value, as shown in table 2. vcell register (0x02) the max17048 measures vcell between the v dd and gnd pins. the max17049 measures vcell between the cell and gnd pins. vcell is the average of four adc conversions. the value updates every 250ms in active mode and every 45s in hibernate mode. soc register (0x04) the ics calculate soc using the modelgauge algorithm. this register automatically adapts to variation in battery size since modelgauge naturally recognizes relative soc. the upper byte least-significant bit has units of 1%. the lower byte provides additional resolution. the first update is available approximately 1s after por of the ic. subsequent updates occur at variable intervals depending on application conditions. table 2. register summary table 1. alert interrupt summary address register name 16-bit lsb description read/write default 0x02 vcell 78.125 f v/cell adc measurement of vcell. r 0x04 soc 1%/256 battery state of charge. r 0x06 mode initiates quick-start, reports hibernate mode, and enables sleep mode. w 0x0000 0x08 version ic production version. r 0x0011 0x0a hibrt controls thresholds for entering and exiting hibernate mode. r/w 0x8030 alert function where configured indicator bit low soc config.athd status.hd soc 1% change config.alsc status.sc reset vreset, status.ri status.vr overvoltage valrt.max status.vh undervoltage valrt.min status.vl
???????????????????????????????????????????????????????????????? maxim integrated products 11 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics figure 8. mode register format table 2. register summary (continued) mode register (0x06) the mode register allows the system processor to send special commands to the ic (see figure 8) . ? quick-start generates a first estimate of ocv and soc based on the immediate cell voltage. use with caution; see the quick-start section. ? ensleep enables sleep mode. ? hibstat is set when the device is in hibernate mode (read only). version register (0x08) the value of this read-only register indicates the production version of the ic. address register name 16-bit lsb description read/write default 0x0c config compensation to optimize performance, sleep mode, alert indicators, and configuration. r/w 0x971c 0x14 valrt configures the vcell range outside of which alerts are generated. r/w 0x00ff 0x16 crate 0.208%/hr approximate charge or discharge rate of the battery. r 0x18 vreset/id configures vcell threshold below which the ic resets itself, id is a one-time factory- programmable identifier. r/w 0x96__ 0x1a status indicates overvoltage, undervoltage, soc change, soc low, and reset alerts. r/w 0x01__ 0x40 to 0x7f table configures battery parameters. w 0xfe cmd sends por command. r/w 0xffff msbaddress 0x06 lsbaddress 0x07 x quick- start ensleep hibstat x x x x x x x x x x x x msb lsb msb lsb
???????????????????????????????????????????????????????????????? maxim integrated products 12 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics hibrt register (0x0a) to disable hibernate mode, set hibrt = 0x0000. to always operate in hibernate mode, set hibrt = 0xffff (see figure 9) . ? actthr (active threshold): if at any adc sample |ocv-cell| is greater than actthr, the ic exits hiber - nate mode and the 6min timer is reset. 1 lsb = 1.25mv. ? hibthr (hibernate threshold). if crate is less than hibthr for longer than 6min, the ic enters hibernate mode. if crate exceeds hibthr, the 6min timer is reset. 1 lsb = 0.208%/hr. config register (0x0c) ? rcomp is an 8-bit value that can be adjusted to optimize ic performance for different lithium chemistries or different operating temperatures. contact maxim for instructions for optimization. the por value of rcomp is 0x97. ? sleep forces the ic in or out of sleep mode. writing 1 forces the ic to enter sleep mode, and 0 forces the ic to exit. the por value of sleep is 0. ? alsc (soc change alert) enables alerting when soc changes by at least 1%. each alert remains until status.sc is cleared, after which the alert automati - cally clears until soc again changes by 1%. do not use this alert to accumulate changes in soc. ? alrt (alert status bit) is set by the ic when an alert occurs. when this bit is set, the alrt pin asserts low. clear this bit to service and deassert the alrt pin. the power-up default value for alrt is 0. the status register specifies why the alrt pin was asserted. ? athd (empty alert threshold) sets the soc threshold, where an interrupt is generated on the alrt pin and can be programmed from 1% up to 32%. the value is (32 - athd)% (e.g., 00000b 32%, 00001b 31%, 00010b 30%, 11111b 1%). the por value of athd is 0x1c, or 4%. the alert only occurs on a fall - ing edge past this threshold. figure 10. config register format figure 9. hibrt register format msb (rcomp)address 0x0c lsbaddress 0x0d rcomp 7 rcomp 6 rcomp 5 rcomp 4 rcomp 3 rcomp 2 rcomp 1 rcomp 0 sleep almd alrt athd 4 athd 3 athd 2 athd 1 athd 0 msb lsb msb lsb msb (hibthr)address 0x0a lsb (actthr)address 0x0b 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb msb lsb hibthr 2 0 unit: 1.25mv actthr 2 0 unit: 0.208%/hr
???????????????????????????????????????????????????????????????? maxim integrated products 13 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics figure 12. vreset/ id register format figure 11. valrt register format valrt register (0x14) this register is divided into two thresholds: voltage alert maximum (valrt.max) and minimum (valrt. min). both registers have 1 lsb = 20mv. the ic alerts while vcell > valrt.max or vcell < valrt.min (see figure 11) . crate register (0x16) the ic calculates an approximate value for the average soc rate of change. 1 lsb = 0.208% per hour (not for conversion to ampere). vreset/id register (0x18) see figure 12. ? id is an 8-bit read-only value that is one-time pro - grammable at the factory, which can be used as an identifier to distinguish multiple cell types in produc - tion. writes to these bits are ignored. ? vreset [7:1] adjusts a fast analog comparator and a slower digital adc threshold to detect battery removal and reinsertion. set between 2.28v and 3.48v, 40mv to 80mv below the applications empty voltage, according to the desired reset threshold for your application. if the comparator is enabled, the ic resets 1ms after vcell rises above the threshold. otherwise, the ic resets 250ms after the vcell reg - ister rises above the threshold. ? dis. set dis = 1 to disable the analog comparator in hibernate mode to save approximately 0.5 f a msb (vreset)address 0x18 lsb (id)address 0x19 2 7 2 6 2 5 2 4 2 3 2 2 2 1 dis id 6 id 5 id 4 id 3 id 2 id 1 id 0 id msb lsb msb lsb vreset 2 0 units: 40mv msb (valrt.min)address 0x14 lsb (valrt.max)address 0x15 min 7 min 6 min 5 min 4 min 3 min 2 min 1 min 0 max 7 max 6 max 5 max 4 max 3 max 2 max 1 max 0 msb lsb msb lsb unit: 20mv
???????????????????????????????????????????????????????????????? maxim integrated products 14 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics status register (0x1a) an alert can indicate many different conditions. the status register identifies which alert condition was met. clear the corresponding bit after servicing the alert (see figure 13). reset indicator: ? ri (reset indicator) is set when the device powers up. any time this bit is set, the ic is not configured, so the model should be loaded and the bit should be cleared. alert descriptors: these bits are set only when they cause an alert (e.g., if config.almd = 0, then md is never set). ? vh (voltage high) is set when vcell has been above alrt.valrtmax. ? vl (voltage low) is set when vcell has been below alrt.valrtmin. ? vr (voltage reset) is set after the device has been reset regardless of envr. ? hd (soc low) is set when soc crosses the value in config.athd. ? sc (1% soc change) is set when soc changes by at least 1% if config.almd is set. enable or disable vreset alert: ? envr (enable voltage reset alert) when set to 1 asserts the alrt pin when a voltage-reset event occurs under the conditions described by the vreset/ id register. table registers (0x40 to 0x7f) contact maxim for details on how to configure these registers. the default value is appropriate for some li+ batteries. to unlock the table registers, write 0x57 to address 0x3f, and 0x4a to address 0x3e. while table is unlocked, no modelgauge registers are updated, so relock as soon as possible by writing 0x00 to address 0x3f, and 0x00 to address 0x3e. cmd register (0xff) writing a value of 0x5400 to this register causes the device to completely reset as if power had been removed (see the power-on reset (por) section). the reset occurs when the last bit has been clocked in. the ic does not respond with an i 2 c ack after this command sequence. application examples the ics have a variety of configurations, depending on the application. table 3 shows the most common system configurations and the proper pin connections for each. in all cases, the system must provide pullup circuits for alrt (if used), sda, and sdl. figure 14 shows an example application for a 1s cell pack. in this example, the alrt pin is connected to the microcontrollers interrupt input to allow the max17048 to signal when the battery is low. the qstrt pin is unused in this application and is connected to gnd. figure 15 shows a max17049 example application using a 2s cell pack. the max17049 is mounted on the system side and powered from a 3.3v supply generated by the system. the cell pin is still connected directly to pack+. figure 13. status register format msbaddress 0x1a lsbaddress 0x1b x envr md hd vr vl vh ri x x x x x x x x msb lsb msb lsb
???????????????????????????????????????????????????????????????? maxim integrated products 15 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics figure 14. max17048 application circuit (1s cell pack) figure 15. max17049 application circuit (2s cell pack) table 3. possible application configurations system configuration ic v dd alrt qstrt 1s pack-side location max17048 power directly from battery leave unconnected connect to gnd 1s host-side location max17048 power directly from battery leave unconnected connect to gnd 1s host-side location, low-cell interrupt max17048 power directly from battery connect to system interrupt connect to gnd 1s host-side location, hardware quick-start max17048 power directly from battery leave unconnected connect to rising-edge reset signal 2s pack-side location max17049 power from +2.5v to +4.5v ldo in pack leave unconnected connect to gnd 2s host-side location max17049 power from +2.5v to +4.5v ldo or pmic leave unconnected connect to gnd 2s host-side location, low-cell interrupt max17049 power from +2.5v to +4.5v ldo or pmic connect to system interrupt connect to gnd 2s host-side location, hardware quick-start max17049 power from +2.5v to +4.5v ldo or pmic leave unconnected connect to rising-edge reset signal v dd alrt sda scl cell qstrt ctg gnd interrupt sda scl system p i 2 c master max17048 battery pack protection 0.1f v dd alrt sda scl cell qstrt ctg gnd interrupt sda scl system p i 2 c master max17049 battery pack protection 0.1f system 2.5v to 4.5v output
???????????????????????????????????????????????????????????????? maxim integrated products 16 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics i 2 c bus system the i 2 c bus system supports operation as a slave-only device in a single or multislave, and single or multimaster system. slave devices can share the bus by uniquely setting the 7-bit slave address. the i 2 c interface con - sists of a serial-data line (sda) and serial-clock line (scl). sda and scl provide bidirectional communica - tion between the ics slave device and a master device at speeds up to 400khz. the ics sda pin operates bidirectionally; that is, when the ic receives data, sda operates as an input, and when the ic returns data, sda operates as an open-drain output, with the host system providing a resistive pullup. the ic always operates as a slave device, receiving and transmitting data under the control of a master device. the master initiates all transactions on the bus and generates the scl signal, as well as the start and stop bits, which begin and end each transaction. bit transfer one data bit is transferred during each scl clock cycle, with the cycle defined by scl transitioning low-to-high and then high-to-low. the sda logic level must remain stable during the high period of the scl clock pulse. any change in sda when scl is high is interpreted as a start or stop control signal. bus idle the bus is defined to be idle, or not busy, when no master device has control. both sda and scl remain high when the bus is idle. the stop condition is the proper method to return the bus to the idle state. start and stop conditions the master initiates transactions with a start condition (s) by forcing a high-to-low transition on sda while scl is high. the master terminates a transaction with a stop condition (p), a low-to-high transition on sda while scl is high. a repeated start condition (sr) can be used in place of a stop then start sequence to terminate one transaction and begin another without returning the bus to the idle state. in multimaster systems, a repeated start allows the master to retain control of the bus. the start and stop conditions are the only bus activities in which the sda transitions when scl is high. acknowledge bits each byte of a data transfer is acknowledged with an acknowledge bit (a) or a no-acknowledge bit (n). both the master and the max17048 slave generate acknowl - edge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low until scl returns low. to generate a no- acknowl - edge (also called nak), the receiver releases sda before the rising edge of the acknowledge-related clock pulse and leaves sda high until scl returns low. monitoring the acknowledge bits allows for detection of unsuccess - ful data transfers. an unsuccessful data transfer can occur if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication. data order a byte of data consists of 8 bits ordered most significant bit (msb) first. the least significant bit (lsb) of each byte is followed by the acknowledge bit. the ic registers composed of multibyte values are ordered msb first. the msb of multibyte registers is stored on even data- memory addresses. slave address a bus master initiates communication with a slave device by issuing a start condition followed by a slave address (saddr) and the read/write (r/w) bit. when the bus is idle, the ics continuously monitor for a start condition followed by its slave address. when the ics receive a slave address that matches the value in the slave address register, they respond with an acknowledge bit during the clock period following the r/w bit. the 7-bit slave address is fixed to 0x6c (write)/0x6d (read): read/write bit the r/w bit following the slave address determines the data direction of subsequent bytes in the transfer. r/w = 0 selects a write transaction with the following bytes being written by the master to the slave. r/w = 1 selects a read transaction with the following bytes being read from the slave by the master ( table 4 ). 0110110 max 17048 /m ax17049 sla ve addre ss
???????????????????????????????????????????????????????????????? maxim integrated products 17 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics table 4. i 2 c protocol key bus timing the ics are compatible with any bus timing up to 400khz. no special configuration is required to operate at any speed. i 2 c command protocols the command protocols involve several transaction formats. the simplest format consists of the master writing the start bit, slave address, r/w bit, and then monitoring the acknowledge bit for presence of the ics. more complex formats, such as the write data and read data, read data and execute device-specific operations. all bytes in each command format require the slave or host to return an acknowledge bit before continuing with the next byte. table 4 shows the key that applies to the transaction formats. basic transaction formats a write transaction transfers 2 or more data bytes to the ics. the data transfer begins at the memory address supplied in the maddr byte. control of the sda signal is retained by the master throughout the transaction, except for the acknowledge cycles: a read transaction transfers 2 or more bytes from the ics. read transactions are composed of two parts, a write portion followed by a read portion, and are therefore inherently longer than a write transaction. the write portion communicates the starting point for the read operation. the read portion follows immediately, beginning with a repeated start, slave address with r/w set to a 1. control of sda is assumed by the ics, beginning with the slave address acknowledge cycle. control of the sda signal is retained by the ics through - out the transaction, except for the acknowledge cycles. the master indicates the end of a read transaction by responding to the last byte it requires with a no acknowl - edge. this signals the ics that control of sda is to remain with the master following the acknowledge clock. write data protocol the write data protocol is used to write to register to the ics starting at memory address maddr. data0 represents the data written to maddr, data1 represents the data written to maddr + 1, and datan represents the last data byte, written to maddr + n. the master indicates the end of a write transaction by sending a stop or repeated start after receiving the last acknowledge bit: the msb of the data to be stored at address maddr can be written immediately after the maddr byte is acknowledged. because the address is automatically incremented after the lsb of each byte is received by the ics, the msb of the data at address maddr + 1 can be written immediately after the acknowledgment of the data at address maddr. if the bus master continues an autoincremented write transaction beyond address 4fh, the ics ignore the data. a valid write must include both register bytes. data is also ignored on writes to read- only addresses. incomplete bytes and bytes that are not acknowledged by the ics are not written to memory. key description key description s start bit sr repeated start saddr slave address (7 bit) w r/w bit = 0 maddr memory address byte p stop bit data data byte written by master data data byte returned by slave a acknowledge bitmaster a acknowledge bitslave n no acknowledgemaster n no acknowledge bitslave r r/w bit = 1 read: s. saddr w. a. maddr. a. sr. saddr r. a. data0. a. data1. n. p write portion read portion write: s. saddr w. a. maddr. a. data0. a. data1. a. p s. saddr w. a. maddr. a. data0. a. data1. a... datan. a. p
???????????????????????????????????????????????????????????????? maxim integrated products 18 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. t = tape and reel. read data protocol the read data protocol is used to read to register from the ics starting at the memory address specified by maddr. both register bytes must be read in the same transaction for the register data to be valid. data0 represents the data byte in memory location maddr, data1 represents the data from maddr + 1, and datan represents the last byte read by the master: data is returned beginning with the msb of the data in maddr. because the address is automatically incre - mented after the lsb of each byte is returned, the msb of the data at address maddr + 1 is available to the host immediately after the acknowledgment of the data at address maddr. if the bus master continues to read beyond address ffh, the ics output data values of ffh. addresses labeled reserved in the memory map return undefined data. the bus master terminates the read transaction at any byte boundary by issuing a no acknowledge followed by a stop or repeated start. package type package code outline no. land pattern no. 8 wlp w80a1+1 21-0555 refer to application note 1891 8 tdfn-ep t822+3 21-0168 90-0065 part temp range pin-package description max17048 g+ -40 n c to +85 n c 8 tdfn-ep* 1-cell modelgauge ic max17048g+t10 -40 n c to +85 n c 8 tdfn-ep* 1-cell modelgauge ic max17048x+ -40 n c to +85 n c 8 wlp 1-cell modelgauge ic max17048x+t10 -40 n c to +85 n c 8 wlp 1-cell modelgauge ic max17049 g+ -40 n c to +85 n c 8 tdfn-ep* 2-cell modelgauge ic MAX17049G+t10 -40 n c to +85 n c 8 tdfn-ep* 2-cell modelgauge ic max17049x+ -40 n c to +85 n c 8 wlp 2-cell modelgauge ic max17049x+t10 -40 n c to +85 n c 8 wlp 2-cell modelgauge ic s. saddr w. a. maddr. a. sr. saddr r. a. data0. a. data1. a... datan. n. p
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 19 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 2/12 initial release 1 4/12 corrected byte-order errors 10, 11, 13 max17048 /max17049 micropower 1-cell/2-cell li+ modelgauge ics

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